The present invention relates to a sense amplifier circuit, and more particularly to a differential sense amplifier having a single-ended output.
Semiconductor memories are of two main types, dynamic memories in which no dc dissipation path is active, and static memories where bistable circuits or the like consume current throughout memory operation. They conventionally have a matrix of complementary pairs of memory elements associated with suitable addressing circuitry. Each pair of complementary memory elements is accessible by a corresponding complementary pair of bit lines A circuit known as a sense amplifier is connectable to the complementary pair of bit lines to determine whether a logic one or logic zero is stored by the pair of memory elements.
Other types of memory circuitry are known in which there is only a single element storing information and in such arrangements it is known for a sense amplifier to compare the level stored in the memory element with that of a reference element so as to judge whether a logical one or a logical zero is stored in the memory element.
Like memory cells, sense amplifiers are of two main types, namely static sense amplifiers and dynamic sense amplifiers. Dynamic sense amplifiers are characterized by a substantial absence of DC current flow between the positive and negative supply lines to the amplifier whereas static sense amplifiers entail such current flow throughout their normal operation.
Known static sense amplifiers comprise circuitry forming a differential-to-single ended amplifier stage which is enabled during the sense operation, the output of which is connected to a cross-coupled latch arrangement which assumes a state determined by the output of the sense amplifier during the sense operation and which retains that state once the sense amplifier is no longer in the sensing mode. Such latch circuitry may be connected to the output of the converter circuit via a transmission gate so as to isolate the output of the converter stage from the input to the latch when the converter stage is inactive.
Providing an additional gate to enable or disable the latch connection has disadvantages, namely provision of additional delays and unnecessary utilization of chip area.
It is accordingly an object of the present invention to at least partially mitigate the difficulties of the prior art.
It is a secondary object of the present invention to provide a sense amplifier circuit having a tristatable output.
According to a first aspect of the present invention there is provided a static sense amplifier circuit having two inputs for connection to complementary bit lines, and an output terminal wherein said circuit comprises control circuitry responsive to a control input for selectively rendering said output terminal high impedance.
According to a second aspect of the present invention there is provided a sense amplifier circuit comprising a first amplifier and a second amplifier, the first amplifier having a pair of differential input nodes and a pair of differential output nodes, the second amplifier having a pair of differential input nodes and a single-ended output node, wherein the pair of differential output nodes of the first amplifier is coupled to the pair of differential input nodes at the second amplifier and the second amplifier has a further input for disabling the second amplifier whereby the output node of the second amplifier may be rendered high impedance.
According to a third aspect of the present invention there is provided sense amplifier circuitry comprising a differential-to-single ended converter and a latch, the converter having an output, the latch having an input and an output, said latch input being coupled to said output of said converter wherein said converter has a control input for causing said output of said converter to assume a high impedance state whereby said latch stores a previous state of said converter.
According to a fourth aspect of the present invention there is provided a sense amplifier circuit comprising a source-coupled pair whose control nodes are coupled to a pair of differential inputs, the drains of said pair being coupled to the control nodes of a further source-coupled pair wherein the common source of the further source-coupled pair is connected via a switched impedance to a negative supply terminal, the drains of the further source-coupled pair are connected to a positive supply via a current mirror circuit and one drain of said further source-coupled pair forms an output terminal.
Conveniently the switched impedance comprises a field effect transistor.
Preferably the source-coupled pair and the further source-coupled pair are n-type transistors.
Advantageously the outputs of the source-coupled pair are further connected to the control electrodes of a pair of transistors whose main current paths are connected between the common source electrodes of the source-coupled pair and a negative supply terminal to provide common mode feedback.
Conveniently the source-coupled pair has a switchable active load.
Preferably the output terminal is connected to a latching circuit.
Conveniently the latching circuit is a latch having a forward path and a feedback path wherein the feedback path is weak compared to the forward path whereby the latch changes state in response to a relatively small input change.